[riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]
Feilong Jiang
fjiang at openjdk.java.net
Wed Jan 12 02:44:55 UTC 2022
On Tue, 11 Jan 2022 08:49:46 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:
>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>>
>> fix build error
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3900:
>
>> 3898: }
>> 3899:
>> 3900: if (shamt == 0) {
>
> Is "shamt == 0" a common condition? Maybe it would be better to move it into the "else" branch.
`shamt == 0` is not a common case. I have moved it to else branch. Thank you for pointing it out :-)
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PR: https://git.openjdk.java.net/riscv-port/pull/43
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