[riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v2]

[Yanhong Zhu]

On Tue, 11 Jan 2022 12:33:27 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> This PR implements shift left and add instructions: `sh1add`/`sh2add`/`sh3add`/`sh1add.uw`/`sh2add.uw`/`sh3add.uw`.
>> 
>> New C2 instructions are covered by JTREG test: test/jdk/java/lang
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   match iRegI instead of iRegIorL2I

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3900:

> 3898:   }
> 3899: 
> 3900:   if (shamt == 0) {

Is "shamt == 0" a common condition? Maybe it would be better to move it into the "else" branch.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/43