[riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]

[Feilong Jiang]

On Wed, 12 Jan 2022 01:44:21 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> This PR implements shift left and add instructions: `sh1add`/`sh2add`/`sh3add`/`sh1add.uw`/`sh2add.uw`/`sh3add.uw`.
>> 
>> New C2 instructions are covered by JTREG test: test/jdk/java/lang
>> 
>> Hotspot and jdk tier1 tests on QEMU (with and without UseRVB) are passed without new failures.
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fix build error

Thanks for the reviews! @yhzhu20 @RealFYang.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/43