[riscv-port] Integrated: 8280116: riscv: RVB: Add rest instructions of zba, zbb, and bitwise rotation

[Feilong Jiang]

On Tue, 18 Jan 2022 07:52:30 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> This PR has the following changes:
> 1. Implement rest instructions of zba, zbb and bitwise rotation sub-extension
> 2. Add non-rvb version of AbsI/AbsL
> 
> Within this PR, zba, zbb and bitwise rotation of RISC-V Bit-Manipulation are fully supported in riscv-port. 
> 
> New C2 instructions are covered by the JTREG tests hotspot:tier1
> 
> Hotspot and jdk tier1 tests on QEMU (with and without UseRVB) are passed without new failures.

This pull request has now been integrated.

Changeset: 21a8e167
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Yanhong Zhu <yzhu at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/21a8e1677d5c8459b895cc85abd64354517f7e45
Stats:     180 lines in 3 files changed: 179 ins; 0 del; 1 mod

8280116: riscv: RVB: Add rest instructions of zba, zbb, and bitwise rotation

Reviewed-by: fyang

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PR: https://git.openjdk.java.net/riscv-port/pull/47