[riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler [v2]

[Yadong Wang]

> The same problem exists on the riscv platfom. So we follow https://bugs.openjdk.java.net/browse/JDK-8276563.
> 
> All instances of type Register exhibit UB in the form of wild pointer (including null pointer) dereferences. This isn't very hard to fix: we should make Registers pointer to something rather than aliases of small integers.
> 
> Hotspot/jdk tier1 were passed on the unmatched board. And all jtreg tests have been tested on Qemu without new failures.

Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:

  fix typo

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Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/53/files
  - new: https://git.openjdk.java.net/riscv-port/pull/53/files/8e61f40c..27ecc023

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=53&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=53&range=00-01

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/53.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/53/head:pull/53

PR: https://git.openjdk.java.net/riscv-port/pull/53