[riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler

[Fei Yang]

On Wed, 26 Jan 2022 05:28:15 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> The same problem exists on the riscv platfom. So we follow https://bugs.openjdk.java.net/browse/JDK-8276563.
> 
> All instances of type Register exhibit UB in the form of wild pointer (including null pointer) dereferences. This isn't very hard to fix: we should make Registers pointer to something rather than aliases of small integers.
> 
> Hotspot/jdk tier1 were passed on the unmatched board. And all jtreg tests have been tested on Qemu without new failures.

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/assembler_riscv.hpp line 46:

> 44:     n_float_register_parameters_c = 8, // f10, f11, ... f17 (c_farg0, c_farg1, ... )
> 45: 
> 46:     n_int_register_parameters_j   = 8, // x11, ... x17, x10 (rj_rarg0, j_rarg1, ...)

Could you please also fix this typo: "rj_rarg0" should be "j_rarg0"? Otherwise looks good. Thanks.

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PR: https://git.openjdk.java.net/riscv-port/pull/53