[riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler [v2]
Feilong Jiang
fjiang at openjdk.java.net
Wed Jan 26 11:11:01 UTC 2022
On Wed, 26 Jan 2022 06:59:35 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:
>> The same problem exists on the riscv platfom. So we follow https://bugs.openjdk.java.net/browse/JDK-8276563.
>>
>> All instances of type Register exhibit UB in the form of wild pointer (including null pointer) dereferences. This isn't very hard to fix: we should make Registers pointer to something rather than aliases of small integers.
>>
>> Hotspot/jdk tier1 were passed on the unmatched board. And all jtreg tests have been tested on Qemu without new failures.
>
> Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
>
> fix typo
Marked as reviewed by fjiang (Author).
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PR: https://git.openjdk.java.net/riscv-port/pull/53
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