[riscv-port-jdk17u:riscv-port] RFR: 8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

[Feilong Jiang]

On Wed, 12 Apr 2023 09:06:13 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> Please review this backport to riscv-port-jdk17u.
> Backport of [JDK-8296447](https://bugs.openjdk.org/browse/JDK-8296447). 
> A little conflict is that we do not have the `vneg_v` in `macroAssembler_riscv.cpp`
> 
> Tested:
> - jdk/incubator/vector (release/fastdebug with UseRVV on QEMU)
> - tier1 (release with UseRVV on QEMU)

Looks good to me.

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Marked as reviewed by fjiang (Author).

PR Review: https://git.openjdk.org/riscv-port-jdk17u/pull/41#pullrequestreview-1382843445