question about vector registers

Vladimir Kempik vladimir.kempik at gmail.com
Tue May 23 06:17:11 UTC 2023


Hello

thank you for explanation

>But currently those usages won't involve v6+ yet
I found one usage of v6+:
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp:

void C2_MacroAssembler::string_compare_v(…)

…
    VectorRegister vstr1 = encLU ? v4 : v0;  //vstr1 could be v4
    VectorRegister vstr2 = encLU ? v0 : v4;

    bind(loop);
    vsetvli(tmp1, cnt2, Assembler::e8, Assembler::m2);
    vle8_v(vstr1, strL);
    vsetvli(tmp1, cnt2, Assembler::e16, Assembler::m4); //lmul=4
    vzext_vf2(vstr2, vstr1);
    vle16_v(vstr1, strU); //usage of v4/v5/v6/v7
…

vstr1 could be v4.

after second vsetvli, we set lmul to 4, so v4 represents also v5, v6, v7

then we load some bytes from memory into vstr1 which stands for v4/v5/v6/v7 combo

I was also able to redo the vector support for vectors 0.7.1 and run it on real hardware ( thead, it has two c910 without vectors and one c910 with vectors, only one of sets can work at a time.), going to prepare some performance results, using openjdk’s microtests.

Regards, Vladimir

> 23 мая 2023 г., в 03:52, yangfei at iscas.ac.cn написал(а):
> 
> Hi,
> 
> Comments inlined.
> 
> > -----Original Messages-----
> > From: "Vladimir Kempik" <vladimir.kempik at gmail.com>
> > Sent Time: 2023-05-23 04:44:38 (Tuesday)
> > To: riscv-port-dev <riscv-port-dev at openjdk.org>
> > Cc: 
> > Subject: question about vector registers
> > 
> > Hello
> > 
> > I have few questions about vector registers usage in hotspot.
> > 
> > Currently there is no calling convention for vector registers [1].
> >
> > Currently all vector registers ( usage in hotspot) are not preserved and volatile ? is it true ?
> 
> Yes, the ABI spec only mentions that vector registers are volatile and are not used for passing arguments or return values for now.
> So if you look at register definition for C2, we set both 'register save type' and 'C convention save type' for vector registers as SOC (Save-On-Call).
> 
> > why do we have defition for v1_reg-v5_reg and the rest of the registers ( except  v0_mask) ?
> 
> Several vector registers (including v0_mask register) are used as scratch registers to optimize code for C2 nodes like ClearArray, StrComp, etc.
> And if you do this, remember to make this explicit on the side effect for those nodes like: https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/riscv_v.ad#L3278
> 
> > I guess some v6+ could be used somewhere due to lmul  = 2 or 4.
> 
> I think it will depend on your specific usage then.
> We already have some use of lmul =2/4 in some C2 assembler functions like C2_MacroAssembler::clear_array_v.
> But currently those usages won't involve v6+ yet.
> 
> Hope that answers the questions,
> Fei Yang
> </riscv-port-dev at openjdk.org></vladimir.kempik at gmail.com>


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