question about vector registers

[yangfei at iscas.ac.cn]

Hi,

Looks like that's not quite right as the usage/clobbering of vector registers v6 and v7 does not menifest in the side-effect of C2 nodes.
We should also add TEMP v6 and TEMP v7 to effect of instructs: vstring_compareU, vstring_compareL, vstring_compareUL and vstring_compareLU.
Let me know if you are interested in fixing this issue.

Thanks,
Fei

-----Original Messages-----
From:"Vladimir Kempik" <vladimir.kempik at gmail.com>
Sent Time:2023-05-23 14:17:11 (Tuesday)
To: yangfei at iscas.ac.cn
Cc: riscv-port-dev <riscv-port-dev at openjdk.org>
Subject: Re: question about vector registers

Hello   
thank you for explanation    
>But currently those usages won't involve v6+ yet
I found one usage of v6+:
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp:    
   
voidC2_MacroAssembler::string_compare_v(…)    
    
    …    
    VectorRegister vstr1 = encLU ? v4 : v0;  //vstr1 could be v4    
    VectorRegister vstr2 = encLU ? v0 : v4;    
    
    bind(loop);    
    vsetvli(tmp1, cnt2, Assembler::e8, Assembler::m2);    
    vle8_v(vstr1, strL);    
    vsetvli(tmp1, cnt2, Assembler::e16, Assembler::m4); //lmul=4    
    vzext_vf2(vstr2, vstr1);    
    vle16_v(vstr1, strU); //usage of v4/v5/v6/v7    
    …    
    
    vstr1 could be v4.    
    
    after second vsetvli, we set lmul to 4, so v4 represents also v5, v6, v7    
    
    then we load some bytes from memory into vstr1 which stands for v4/v5/v6/v7 combo    
    
    I was also able to redo the vector support for vectors 0.7.1 and run it on real hardware ( thead, it has two c910 without vectors and one c910 with vectors, only one of sets can work at a time.), going to prepare some performance results, using openjdk’s microtests.    
    
    Regards, Vladimir    

</riscv-port-dev at openjdk.org></vladimir.kempik at gmail.com>