[riscv-port] RFR: 8282331: is_wide_vector should not depend on specific vector size [v2]

[Feilong Jiang]

> On RISC-V, vector registers should always be saved when RVV is enabled.
> 
> Tier1 tests on QEMU with UseRVV enabled are passed without new failures.

Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:

  8282331: riscv: is_wide_vector should not depend on specific vector size

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Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/59/files
  - new: https://git.openjdk.java.net/riscv-port/pull/59/files/7d740b4a..7a177a30

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=59&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=59&range=00-01

  Stats: 0 lines in 0 files changed: 0 ins; 0 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/59.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/59/head:pull/59

PR: https://git.openjdk.java.net/riscv-port/pull/59