[riscv-port-jdk17u:riscv-port] RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]

[Fei Yang]

On Wed, 7 Jun 2023 07:55:16 GMT, Gui Cao <gcao at openjdk.org> wrote:

>> Hi,
>> Please help review this backport to riscv-port-jdk17u.
>> Backport of [JDK-8308997](https://bugs.openjdk.org/browse/JDK-8308997). 
>> Because there is no [JDK-8294100](https://bugs.openjdk.org/browse/JDK-8294100), [JDK-8301496](https://bugs.openjdk.org/browse/JDK-8301496) here in riscv-port-jdk17u, it will show not clean.
>> 
>> Testing:
>> 
>> Tier1-3 passed without new failure on unmacthed (release).
>
> Gui Cao has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Use sign_extend instead addw in move32_64

Looks good.

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Marked as reviewed by fyang (Lead).

PR Review: https://git.openjdk.org/riscv-port-jdk17u/pull/67#pullrequestreview-1468958150