June 2023 Archives by subject

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Starting: Thu Jun 1 01:20:35 UTC 2023
Ending: Thu Jun 22 14:02:23 UTC 2023
Messages: 27

• [riscv-port-jdk17u:riscv-port] Integrated: 8301033: RISC-V: Handle special cases for MinI/MaxI nodes for Zbb   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] Integrated: 8301818: RISC-V: Factor out function mvw from MacroAssembler   Gui Cao
• [riscv-port-jdk17u:riscv-port] Integrated: 8302289: RISC-V: Use bgez instruction in arraycopy_simple_check when possible   Gui Cao
• [riscv-port-jdk17u:riscv-port] Integrated: 8305008: RISC-V: Factor out immediate checking functions from assembler_riscv.inline.hpp   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] Integrated: 8305728: RISC-V: Use bexti instruction to do single-bit testing   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] Integrated: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit   Gui Cao
• [riscv-port-jdk17u:riscv-port] Integrated: 8309427: [riscv-port-jdk17u] Remove unused RoundDoubleModeV C2 node   Gui Cao
• [riscv-port-jdk17u:riscv-port] RFR: 8301033: RISC-V: Handle special cases for MinI/MaxI nodes for Zbb   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] RFR: 8301033: RISC-V: Handle special cases for MinI/MaxI nodes for Zbb   Fei Yang
• [riscv-port-jdk17u:riscv-port] RFR: 8301033: RISC-V: Handle special cases for MinI/MaxI nodes for Zbb   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] RFR: 8305728: RISC-V: Use bexti instruction to do single-bit testing   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] RFR: 8305728: RISC-V: Use bexti instruction to do single-bit testing   Feilong Jiang
• [riscv-port-jdk17u:riscv-port] RFR: 8305728: RISC-V: Use bexti instruction to do single-bit testing   Fei Yang
• [riscv-port-jdk17u:riscv-port] RFR: 8305728: RISC-V: Use bexti instruction to do single-bit testing   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] RFR: 8305728: RISC-V: Use bexti instruction to do single-bit testing   Fei Yang
• [riscv-port-jdk17u:riscv-port] RFR: 8305728: RISC-V: Use bexti instruction to do single-bit testing   Dingli Zhang
• [riscv-port-jdk17u:riscv-port] RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit   Gui Cao
• [riscv-port-jdk17u:riscv-port] RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]   Gui Cao
• [riscv-port-jdk17u:riscv-port] RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]   Fei Yang
• [riscv-port-jdk17u:riscv-port] RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]   Gui Cao
• [riscv-port-jdk17u:riscv-port] RFR: 8309427: [riscv-port-jdk17u] Remove unused RoundDoubleModeV C2 node   Gui Cao
• [riscv-port-jdk17u:riscv-port] RFR: 8309427: [riscv-port-jdk17u] Remove unused RoundDoubleModeV C2 node   Fei Yang
• [riscv-port-jdk17u:riscv-port] RFR: 8309427: [riscv-port-jdk17u] Remove unused RoundDoubleModeV C2 node   Gui Cao
• git: openjdk/riscv-port-jdk17u: riscv-port: 13 new changesets   duke
• git: openjdk/riscv-port-jdk17u: riscv-port: 2 new changesets   duke
• git: openjdk/riscv-port-jdk17u: riscv-port: 50 new changesets   duke
• git: openjdk/riscv-port-jdk17u: riscv-port: 9 new changesets   duke

Last message date: Thu Jun 22 14:02:23 UTC 2023
Archived on: Thu Jun 22 14:02:28 UTC 2023

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